1. Field of the Invention
The present invention relates to temperature compensating circuits. More particularly, the invention relates to a temperature compensating circuit operable to provide a single clock domain for analog-to-digital converter outputs.
2. Description of the Related Art
Analog-to-digital converters (ADCs) are utilized in innumerable environments to convert analog signals to digital signals. Although ADCs are operable to rapidly convert analog signals to digital signals, the performance of ADCs, including calculation and throughput latency, is dependent upon temperature. For instance, as temperature increases or decreases, throughput latency increases and decreases, respectively, by a corresponding amount. Such variations in ADC performance often have a substantial and detrimental impact on system usage, particularly in high speed configurations.
Devices have been developed to attempt to compensate for variations in ADC performance caused by temperature changes. As shown in FIG. 1, these devices typically require the utilization of at least one first-in-first-out (FIFO) buffer for each ADC output and a plurality of independent clock domains. Specifically, a first clock domain is utilized for sampling by the ADCs, a second clock domain is utilized by the FIFO buffers, and a third clock domain is utilized by filters or other elements coupled with the FIFO buffers.
Unfortunately, utilization of a plurality of FIFO buffers and multiple clock domains requires additional component space, increases routing and design complexity, and increases heat generated by the system. Thus, systems are often unable to utilize FIFO buffers or other conventional methods and devices to compensate for ADC temperature variations.